NXP Semiconductors /LPC176x5x /SYSCON /PLL0CFG

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Interpret as PLL0CFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MSEL00 (RESERVED)RESERVED 0NSEL00 (RESERVED)RESERVED

Description

PLL0 Configuration Register

Fields

MSEL0

PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware.

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NSEL0

PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32.

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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